A memory device or memory can generally be described as hardware that can store data for later retrieval. A clock buffer is an important element in memory operation. One purpose of the clock buffer is to produce a control clock for the memory from an external clock.
When the memory is accessed for read or write purposes, an internal clock signal provides synchronous timing within the memory. This internal clock signal is separate from the external clock of the circuitry that may be attached to the memory. Placing a complete clock generator within the memory is an expensive solution and occupies a large area of circuitry. Therefore, conventional memory uses a clock buffer to generate the internal memory clock from an external circuitry's clock. The internal memory clock controls timing of events such as latching memory addresses, bit line pre-charging, and selecting word lines.
A conventional clock buffer accepts an input clock signal as well as other signals from external circuitry and generates an output clock (internal memory clock) signal under certain combinations of the input signals. In a conventional clock buffer, a clock driver couples to the input clock signal as well as a delayed clock signal and outputs an intermediate clock signal. The clock driver generally has several transistors including a pFET configured to pull up the intermediate clock signal upon a reset signal and nFETs in series configured to pull-down upon a combination of a clock signal, delayed clock signal, and chip select signal. The intermediate clock signal is buffered through the use of a keeper circuit including two inverters. A clock inverter generates the output clock signal from the intermediate clock signal.
Shrinking transistor elements to 45 nm and below, reducing supply voltages to facilitate the smaller transistors, and a desire for lower power consumption have created multiple problems with conventional clock buffer circuitry found in memory.
One problem is that the pull down path of the clock generator is enabled by the external clock and disabled by a hard delay of the same external clock. The delay is required to ensure that the output of the clock generator is already pulled down when pull down by the clock generator is disabled. If the delay is not long enough, the clock generator will fail resulting in failure of the entire clock buffer circuit to output the desired internal memory clock.
Another problem lies in the use of the previously described delay. During the delay, the chip select line must stay low. The time the chip select line must stay low is the hold time and must be longer than the clock delay implemented in the circuit. The clock delay is on the order of 100-1000 picoseconds and commonly 300 picoseconds. The length of the hold time also affects the setup time for inputs to the memory latches. Use of a delay circuit in the clock buffer can cause timing violations leading to unstable memory operation. Moreover, the length of the optimal delay time varies across PVT conditions. Thus, the delay is often set longer than the minimum time required under ideal conditions. Consequently, the clock delay can be problematic.
A third problem in the conventional design is the use of two nFET transistors in the pull-down circuit. Two nFETs are used to perform the logic function of combining the clock and the delayed clock signals. nFETs are relatively large devices that require increased circuit area and, therefore, decrease the storage density of the memory. Additionally, the capacitance of the two nFETs increases the load on the external clock.
A fourth problem lies in the use of a latch in the keeper circuit of the conventional clock buffer circuit. The clock generator contends with the keeper circuit to change the memory clock from low to high or high to low. Under certain process conditions, such as low supply voltage or low temperature, the clock generator may not be capable of changing the output clock. Conventional supply voltages are over one volt and some are now less than one volt. Supply voltages in the range of 0.8-0.9 volts lead to conventional clock buffer failure. A failure of this type results in an incorrect output clock signal and failure in the memory circuitry.
Thus, there is a need for an improved clock buffer.